Cross-monitored pair of clocks for processor fail-safe operation
US5301171A · kind A · utility
12Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1993 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jun 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for operating a pair of microprocessors with independent system clocks while at the same time providing synchronization by a common interrupt signal, and in which the system clocks are cross-monitored to thereby provide Fail-Safe operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.