Data processor apparatus and method with selective caching of instructions
US5301295A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1991 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | May 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether it is a program memory data access (PMDA) instruction that requires a data transfer from the program memory when the next instruction is fetched from the program memory. If it is a PMDA instruction, the next instruction is loaded into a cache, which then provides the stored instruction each time the PMDA instruction reappears. This relieves a bottleneck resulting from a simultaneous call for both the next instruction, and datum for the current instruction, from the program memory. The cache is used only for an instruction following a PMDA instruction, and can thus have a substantially smaller capacity than previously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.