Processor for multiple cache coherent protocols
US5301298A · kind A · utility
31Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.