Double unequal bus timeout
US5301329A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 1990 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jul 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement for preventing the locking out of devices which are coupled to a bus by either of two of the devices which have become initiator and target devices respectively. The devices arbitrate for control of the bus after the bus enters a bus free phase. The device which wins the arbitration becomes an initiator. A timer in each device on the bus is started upon the initiation of the arbitration. The initiator device is removed from the bus when an elasped time after the timers have been started reaches a pre-determined value. The distributed clock of the invention ensures that the devices coupled to the bus will clear the bus after the initiator has been on the bus for a pre-determined time, thereby obviating skew problems associated with single clocked systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.