Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US5301344A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1991 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jan 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.