Computer connection circuit in facsimile
US5303067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1991 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Nov 21, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0034
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a computer connection circuit in a facsimile, comprising: control and memory unit including CPU(Central Processing Unit)(11a), RAM(Random Access Memory)(11c), and ROM(Read Only Memory)(11b) for controlling a general operation control of the facsimile; address decoder 12 connected to the control and memory unit through an address bus, for selecting and enabling an output terminal according to an input address; a modem 31 connected to the control and memory unit through a date bus and connected to communication lines, in which is driven by a first chip selection signal of the address decoder 12 and requires an interrupt to the control and memory unit in sending/receiving image information; and an UART51(Universal Asynchronous Receiver & Transmitter) connected to the control and memory unit and to RS232C interface means of the computer, in which requites an interrupt to the control and memory unit in sending/receiving image and character information to/from the computer and is driven by a second chip selection signal of the address decoding decoder 12.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.