Pipelined combination and vector signal processor
US5303172A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1988 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Feb 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital array signal processor and an associated method are described for implementing the fast Fourier transform radix-4 butterfly algorithm. The digital array signal processor is an integrated circuit with a four stage pipeline and can perform a radix-4 butterfly operation on four complex operands every 80 nanoseconds. Using the decimation-in-frequency implementation of the radix-4 butterfly algorithm, the digital array signal processor includes a first stage for distribution of complex input operand values, a second stage for performing addition and subtraction operations, a third stage for performing multiplication operations and a fourth stage for distribution of the output operand values. The digital array signal processor can be reconfigured to perform a radix-2 butterfly operation on two sets of two complex numbers during the 80 nanosecond machine cycle as well as frequently used arithmetic and logic operations. The digital signal array processor can be configured to perform a series of operations on an array of operands or can be one of a series of processors, each processor performing a separate operation on an operand array. According to a second implementation, the di…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.