High performance array multiplier using four-to-two composite counters
US5303176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1992 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Jul 20, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for the reduction of partial products of a multiplier combines attributes of pre-addition and the regularity found in array multipliers by employing improved four-to-two composite counter cells. This composite counter cell, the basic block for reducing the partial products, is itself comprised of two new four-to-two counters. One of the four-to-two counters is used to perform pre-addition of the partial products while the second counter is used to perform addition between the sum produced by the counter performing the pre-addition and the outputs from the second counter of a cell in a previous stage of the addition. The regularity of array multiplication schemes is preserved and interconnections required by the mechanism span no more than two columns of the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.