Semiconductor memory device having information indicative of presence of defective memory cell
US5303192A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1992 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Feb 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device storing data having a unit of N bits (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying one-bit data and connected to a corresponding one of the M memory elements. A designating circuit receives an address signal from an external device and designates one of the plurality of blocks of each of the M memory elements so that M blocks are designated by the address signal. A ROM stores information on whether or not each of the plurality of blocks of each of the M memory elements has a defective memory cell and outputs the information in accordance with the address signal. N external bus lines individually carry one-bit data. A bus line switching circuit determines whether each of the M blocks designated by the designating circuit has a defective memory cell by referring to the information from the ROM, and selectively connects N internal bus lines among the M internal bus lines to the N external bus lines so that one of the M blocks which has a defective memory cell is prevented from …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.