Clock generation in a multi-chip computer system
US5303365A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1991 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Jun 14, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a multi-chip computersystem with master-slave latches. It is known to provide all latches on all chips with two clock pulses, respectively. With the help of the latches the digital signals are pipelined through the logic gates on the chip. Due to tolerances, the edges which control the masters and the slaves have a skew. According to the invention, one of the two clock pulses is generated on the chip itself, respectively, by ANDing an auxiliary clock pulse with the other of the two clock pulses. This has the result, that the above mentioned edges of the two clock pulses occur almost at the same time with the consequence that the frequency of the clock pulses can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.