TTL/CMOS input buffer operable with three volt and five volt power supplies
US5304872A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1992 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Aug 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual mode input buffer having two modes of operation, a first mode of operation which provides a first CMOS level output from a TTL level input while operating at a first voltage level, and a second mode of operation which provides a second CMOS level output from a TTL level input while operating at a second voltage level. A first input provides TTl level inputs. An output provides a first CMOS level output and a second CMOS level output, one at at a time, depending on the mode of operation. A second input selects one of the two operation modes. Buffer means provides buffering of the signals provided on the first input. The buffer means has a level shifting transistor. Trip point level shifting means is provided for maintaining the trip point of the dual mode input buffer at approximately the same voltage level when the dual mode input buffer is operated at the second voltage level as when it operates at the first voltage level. A second input activates said trip point level shifting means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.