Lock sensor circuit and method for phase lock loop circuits
US5304952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1993 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | May 10, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal. A lock logic circuit (TLATCH, BLATCH, 64, 66, G7) is coupled through NAND gates (G1, G2) to outputs of the respective first down counter (F1, F2) and second up counter (F3,F4). The lock logic circuit generates an u…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.