Low noise high speed frequency synthesizer employing a learning sequence
US5304956A · kind A · utility
9Cited by
3References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1992 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Jul 17, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an apparatus and method for high speed tuning to a commanded frequency using a low noise high speed frequency synthesizer employing a learning sequence. A phase-locked loop (PLL) generates the commanded frequency. High speed tuning circuitry high speed tunes the PLL to the commanded frequency. Thereafter, the high speed tuning circuitry is substantially isolated from the PLL, while learning circuitry is employed to learn a correction signal which will enable subsequent more accurate high speed tuning to the commanded frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.