High speed parallel test architecture
US5305266A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1991 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Mar 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a circuit comprising: a plurality of memory cells (not shown); a plurality of first amplifiers (each first amplifier is preferably comprised of; a plurality of sense amplifiers (e.g. 20), a block amplifier (e.g. 22), and a second means, preferably a block-I/O pair (e.g. 24 and 26), to connect the plurality of sense amplifiers to the block amplifier), wherein each first amplifier is selectively connected, preferably by a bitline pair (not shown), to a portion of the plurality of memory cells; a second amplifier (e.g. 34 in FIG. 2) connected to the plurality of first amplifiers by a first means, preferably a local-I/O pair (e.g. 28 and 32); and a means of comparing data, preferably determining whether the data are comprised of the same data states on the first means, from the selectively connected portions of the plurality of memory cells with data from the remainder of the selectively connected portions of the plurality of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.