Address input buffer
US5305282A · kind A · utility
19Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 24, 1992 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Apr 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address input buffer of a semiconductor memory device comprises an address input terminal, a column address switch, a row address switch, a column address latch connected to the column address switch, a row address latch connected to the row address switch, and an input buffer connected to the address input terminal, and the common node of the column address switch and the row address switch and controlled by an input buffer control signal. Thus, layout area can be reduced by buffering the row and column address input signals with one input buffer without separating the column and row address buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.