Multi chip module substrate
US5306546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1992 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Dec 22, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-level substrate (24) for mounting and interconnecting a number of integrated circuit chips (10) is formed of a stack of laminated sheets each comprising a conductive circuit layer (30,34,38,42,46) is laminated to a dielectric film (32,36,40,44,48). The sheets are formed by fully additive or semi-additive processes on a reusable mandrel and are interconnected to one another by raised features (78) on the circuit layer of one sheet that project through a hole (86) in the dielectric film of an adjacent sheet to contact a receiving area (88) of the circuit layer of the adjacent sheet. Integrated circuit chips (10) and other electrical components are mounted to the uppermost sheet and electrically connected thereto by means of wiring bonding (16) or a f lip-chip arrangement (150) in which chip pads (148) rest upon and contact raised features (146) of the circuit layer (140) of the uppermost sheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.