Semiconductor device having a passivation layer with silicon nitride layers
US5306946A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is protected by a passivation layer, which includes underlying and overlying silicon nitride layers deposited by the plasma-assisted CVD method by changing layer forming conditions. The silicon nitride layers respectively have their intrinsic compressive stresses. The underlying silicon nitride layer in contact with a metal wiring layer has the intrinsic compressive stress of 3.times.10.sup.9 to 1.times.10.sup.10 dyne/cm.sup.2. The overlying silicon nitride layer has the intrinsic compressive stress which is less than or equal to half of the intrinsic compressive stress of the underlying silicon nitride layer. The underlying and overlying silicon nitride layers have different degrees of the hydrogen content. The underlying silicon nitride layer has the hydrogen content of 0.5.times.10.sup.20 to 5.times.10.sup.21 atm/cm.sup.3. The overlying silicon nitride layer has the hydrogen content which is more than or equal to twice of the hydrogen content of the underlying silicon nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.