Binary controlled digital tapped delay line
US5306971A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 1992 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Jul 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00228
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic, binary-controlled digital tapped delay line is realized by a plurality of like stages connected in cascade. Each stage comprises a differential amplifier circuit responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair. A first loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading effect is connected to an input of a first transistor of the differential transistor pair for delaying turn-on of the first transistor. Similarly, a second loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading is connected to an input of a second transistor of the differential transistor pair for delaying turn-on of the second transistor, the first and second loading circuits each being connected to a first circuit node. A delay control circuit is responsive to a binary control signal and connected to the first circuit node for causing turn-on of the first and second transistors to be delayed by a set amount of time when the binary control signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.