Two stage accumulator for use in updating coefficients
US5307375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1992 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Nov 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two stage accumulator is provided for updating coefficients. The accumulator is particularly useful in an adaptive equalizer. A first stage of the accumulator receives an error word and outputs sign and carry bits resulting from the addition of the error word and an N-bit LSB portion of a larger M-bit coefficient. A second stage is responsive to the sign and carry bits for updating the (M-N) MSB's of the M-bit coefficient. New error words are cyclically provided to the first stage during successive coefficient update cycles. The first stage can be implemented using an N-bit twos complement adder. The second stage can be implemented using an up/down counter. A leakage function is provided by causing the up/down counter to periodically skip over increment and decrement cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.