Two-level cache memory system
US5307477A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1993 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | May 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.