Data processing system having multiple register management for call and return operations
US5307502A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1992 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Sep 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating main memory is provided in the same instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.