Semiconductor memory device and method for controlling its output
US5309398A · kind A · utility
20Cited by
1References
5Claims
0Family size
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Key dates
| Filing date | Sep 24, 1992 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Sep 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.