Conductor capacitance reduction in integrated circuits
US5310700A · kind A · utility
84Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1993 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Mar 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passive semiconductor structure for reduction of the mutual capacitance between parallel conductors, with two parallel conductors separated from a substrate by a first dielectric layer and covered by a second dielectric layer. The second dielectric layer having a cavity formed between these conductors, whereby the effective relative dielectric constant of the medium between these conductors is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.