Process for fabricating an integrated circuit device by forming a planarized polysilazane layer and oxidizing to form oxide layer
US5310720A · kind A · utility
56Cited by
6References
10Claims
0Family size
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Key dates
| Filing date | Feb 24, 1993 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Feb 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thick planarization layer of silicon dioxide that is heat resistant is provided by coating a polysilazane layer over a substrate having steps and firing the polysilazane layer in an oxygen-containing atmosphere to convert the polysilazane to silicon dioxide. The temperature of this conversion may be as low as 400.degree. to 450.degree. C. while a higher firing or curing temperature is preferable to obtain a more densified oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.