Level shifting CMOS integrated circuits
US5311075A · kind A · utility
4Cited by
6References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Aug 13, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level shifter circuit includes a pair of CMOS invertors having inputs and outputs cross connected thereto. One of a pair of power source terminals of each of the CMOS invertors is grounded, and complementary input signals are supplied to the CMOS invertors by way of the other power source terminals, and output signals are taken out from output terminals of the CMOS invertors. The voltage level shifter circuit level shifts an input amplitude substantially equal to an input threshold value of transistors to the voltage level of the power source while suppressing the dc consumption current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.