Data bus using open drain drivers and differential receivers together with distributed termination impedances
US5311081A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Apr 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An open drain driver, differential receiver circuit for transmitting logic signals generated by metal oxide semiconductor (MOS) logic circuits over a data bus that uses distributed termination impedances. The distributed termination impedance values are chosen to minimize the data bus settling time both when a driver in a given module drives a signal consisting of alternating logic levels, as well as when two different drivers drive a given logic level in succession. Each open drain driver includes a multiplexor, a flip flop, an inverter stage, and a driver transistor. The multiplexor selects either a data signal to be transmitted or a deasserted data value to be passed to the input of the flip flop. The flip flop also accepts a test input, which sets the flip flop to a known state. As a result, no additional delay is inserted in the critical path between the rising edge of a flip flop clock input signal and the driver output. The companion differential receiver receives a reference voltage which is separately generated on each module, to permit the use of distributed power supplies while still adjusting for variations which may exist in a termination voltage from module to module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.