Semiconductor memory, components and layout arrangements thereof, and method of testing the memory
US5311476A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 18, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Jun 18, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.