Synchronous type semiconductor memory
US5311483A · kind A · utility
187Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1993 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Apr 12, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM is capable of regulating an output timing of a read data. The output timing of the read data can be regulated by the DRAM which has a circuit (127) for counting the number of clock pulses until the read data is transferred to a data latch circuit (121) and a circuit (129) for outputting the counted number. The DRAM has a circuit (125) which can regulate the output timing in response to an external input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.