Multiplexer
US5311519A · kind A · utility
11Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Apr 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A multiplexer circuit which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.