Method and apparatus for implementing post-modulation error correction coding scheme
US5311521A · kind A · utility
Inventors
Key dates
| Filing date | Jan 12, 1990 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Jan 12, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of and apparatus for providing error correction coding for a block of user data in which the user data is initially modulated by a first modulator and then the modulated user data is error correction encoded to produce a first plurality of check bits. The first plurality of check bits are then modulated by a second modulator whose output is then fed to a second error correction encoder which produces a second plurality of check bits. The modulated user data, the first plurality of check bits and the second plurality of check bits are all fed to a shift register where the error correction encoded user data block is formed, useful with magnetic and optical storage devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.