Semiconductor power device having walls of an inverted mesa shape to improve power handling capability
US5313092A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Mar 3, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/012
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.