Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols
US5313464A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | May 5, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A symbol interleaving method for organizing data in a semiconductor memory such that fault tolerance of the memory is optimized when used in conjunction with a Reed-Solomon burst error correcting code. The Reed-Solomon symbols are aligned with respect to the bus bits of the memory such that the impact of a bus bit failure that affects all memory devices in the memory using the bus is constrained within the correction capability of the ECC. The symbols also are distributed among the memory devices in order to maximize fault tolerance. Up to two memory devices in the preferred embodiment may fail without exceeding the correction capability of the code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.