Method and apparatus for deskewing digital data
US5313501A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Jun 15, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a computer system, parallel streams of digital data are transmitted from a source to a destination in bursts or packets. At the beginning of each burst all the parallel data signals contain a start bit. Each data signal is received by a deskewing buffer which transmits the data signal through a delay line with multiple taps. At the beginning of each clock cycle the signal value Data(i) at each tap (i) in the delay line is latched. Each resulting latched signal value LData(i) is compared with the latched signal value LData(i+1) for the next tap down the delay line to generate a set of comparison signals C(i). When the start bit of a new burst is received, one of the comparison signals will have a distinct value from all the others, thereby indicating the delay line tap at which the phase of the received data signal is approximately synchronized with the receiver's clock signal. The data stored in the deskewing buffer's latches represents the phase of the received digital signal and is retained until the end of the burst transmission. A multiplexer which outputs a selected one of data signals from the tapped delay line in accordance with the values of the comparison signals. The s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.