Multiple I/O processor system
US5313584A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1991 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Nov 25, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention involves the use of multiple I/O processors (204) and (206), configured in parallel in an I/O system (104), to increase system performance as well as enhance system resiliency. Performance is increased by programming one of the multiple I/O processors with the added ability to allocate received I/O job requests among the active I/O processors including itself, thus allowing for parallel processing. The I/O system resiliency is enhanced by ensuring that any one of the I/O processors can assume the tasks of any other I/O processor which may fail. The I/O system described above employs a load balancing algorithm to evenly distribute the I/O job functions among the active I/O processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.