Computer bus arbitration for N processors requiring only N unidirectional signal leads
US5313591A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Jun 25, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for using N unidirectional lines to implement signals for arbitration, variable length transactions, automatic responses, and efficient burst transaction modes for a bus in a cache-coherent multi-processor computer system having N processors. Processors use arbitration lines to implement busy signals for variable length transactions. A processor needing to respond to a transaction is granted automatic access to a bus if it is the last processor asserting a busy signal. A processor in a burst transaction mode is granted automatic continuous access without arbitration if no other processors request access. The use of only N lines minimizes pin-out for an integrated processor. The use of unidirectional (one driver, N-1 receivers) lines further optimizes cost and speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.