System for detecting boundary cross-over of instruction memory space using reduced number of address bits
US5313606A · kind A · utility
6Cited by
9References
1Claims
0Family size
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Key dates
| Filing date | Jan 17, 1991 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Jan 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.