Peak hold circuit with improved linearity
US5315168A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | May 24, 1994 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/04
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A peak hold circuit includes an operational amplifier in a continually closed feedback loop and a peak hold capacitor with a discharge path. An input signal is received at a first input of the amplifier, and the output of the amplifier is fed to a first transistor then fed back therefrom to a second input of the amplifier. A current sink is coupled to the first transistor for drawing a current therefrom so that the feedback signal is continually provided to the second amplifier input, ensuring that the amplifier is in a continually closed feedback loop. The output of the amplifier is supplied to the peak hold capacitor through a second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.