Active surge rejection circuit
US5315651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1993 |
| Grant date | May 24, 1994 |
| Priority date | — |
| Expiry date | Jun 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/18
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The ACTIVE SURGE REJECTION CIRCUIT uses a FET connected in one of the TIP and RING leads to open and close the lead. A JK flip-flop is connected to a voltage sensing circuit which senses voltage surges and clocks the flip-flop early in the voltage rise. This activates a first circuit to ground the FET gate and hold the FET open. Meanwhile, a second circuit comprising an RC circuit charges a capacitor which maintains the FET in its OFF condition for a period of time longer than the surge, i.e., about 1 m sec, and then clears the JK flip-flop after the capacitor has discharged a predetermined amount. This invention thus provides surge (noncommon mode) protection, and is especially useful in protecting modems from voltage surges while minimizing signal distortion during non-surge conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.