Method of sequencing bus operations in a simplex switch
US5317565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1993 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Jan 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/445
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sequencing scheme is provided for prioritizing bus operations occurring in simplex switches which interconnect subsystems in a data communications system, thereby yielding improved aggregate system data throughput. The sequencing scheme provides procedures which simultaneously accommodate (i) concurrently pending requests to a first control bus which processes only circuit switched operations and (ii) concurrently pending requests to a second control bus which processes only packet switched operations, in an order which optimizes link level control message throughput of the simplex switch. The control messages which are coordinated by the sequencing scheme include connect and disconnect requests, connect and disconnect request acknowledgments, and data acknowledgments. All connect request and disconnect requests are managed by a connection processing (CP) bus, which operates as a circuit switching bus, and all data acknowledgments and connect request acknowledgments from subsystems attached to a cascaded switch are made over an out-of-band (OB) bus, which operates as a packet switching bus. Because connect and disconnect operations over the CP bus can proceed independently of ack…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.