Processor system with writeback cache using writeback and non writeback transactions stored in separate queues
US5317720A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1993 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Mar 22, 2013 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.