Minimal interrupt latency scheme using multiple program counters
US5317745A · kind A · utility
16Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 10, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Jan 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for using multiple program counters to reduce the latency time of a computer in response to an interrupt or subroutine call using a memory with multiple memory locations for storing the multiple program counters and control means in order to choose which one of the memory locations is used as a current program counter. Additionally, the use of a memory location to store the starting address of the interrupt subroutine is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.