Manufacturing method of thin film transistor
US5318919A · kind A · utility
35Cited by
7References
2Claims
0Family size
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Key dates
| Filing date | Jul 30, 1991 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Jul 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a thin film transistor, wherein a laminated body consisting of an intrinsic amorphous silicon layer and a conductive amorphous silicon layer is formed on a glass substrate, and annealed at low temperatures not higher than 600.degree. C. thereby obtaining a polycrystalline silicon film. The conductive amorphous silicon layer gives girth to a core for polycrystallization, and therefore the intrinsic amorphous silicon layer is easily recrystallized by annealing at low temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.