Integrated circuit device having a geometry to enhance fabrication and testing and manufacturing method thereof
US5319224A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Aug 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.