Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
US5319260A · kind A · utility
40Cited by
17References
6Claims
0Family size
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Key dates
| Filing date | Oct 20, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Oct 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS device having many output channels at least one of which channel includes a first pair of pull-up/pull-down of transistors between a "noisy Vcc and noisy ground", a second pair of pull-up/pull-down of transistors between a "quiet Vcc and quiet ground", and logic to switch the transistor pairs such that initial switching of an output is powered by the noisy Vcc and ground, and maintenance of an output state is powered by the quiet Vcc and ground. Quiescent channels are decoupled from active channels and will hold their assigned output levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.