Low power TTL/CMOS receiver circuit
US5319262A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1993 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Feb 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power TTL/CMOS receiver circuit consists of four stages, each of which is, respectively, comprised of at least two complementary FET devices connected to each other in series. The various stages control each other by a variety of feedback interconnections. The use of feedback loops permits to significantly decrease the DC current in the input stage of the receiver circuit. It also realizes a substantial decrease in AC current consumption, although less significantly. Finally, delay variations between input and output signals are obtained as well as substantial improvements in the symmetry between the true and complement output signals of the receiver circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.