Clocking system for asynchronous operations
US5319678A · kind A · utility
15Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Mar 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.