Queued interrupt mechanism with supplementary command/status/message information
US5319753A · kind A · utility
76Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Sep 29, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.