Slave controller for effecting a block transfer of sixteen bit words between a memory and a data transfer bus
US5319767A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Aug 25, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A slave controller with block transfer capability for transferring data blocks of between one and two hundred fifty six sixteen bit words between a memory and the VERSA MODULE EUROPE bus (VMEbus). The slave controller comprises a programmable array logic device which receives control and address modifier signals from the VMEbus and an address enable signal from a decoding circuit which provides the address enable signal to the programmable array logic device in response to an address strobe signal provided by the VMEbus. The programmable array logic device being responsive to these signals enables the memory for a read or write operation. The programmable array logic device next provides a write pulse to the memory when data is to be written into the memory at addresses provided by a binary counter. When data is to be read from the memory, the programmable array logic device maintains the memory's write enable input at an inactive state and generates an output enable pulse allowing data to be read from the memory at addresses provided by the binary counter. The first address for a block transfer of data is provided by the VMEbus to the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.