Integrated circuit via structure
US5321211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1992 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Apr 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.