Programmable interconnect architecture without active devices
US5321322A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1993 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Mar 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated, user-programmable interconnect architecture, includes a plurality of input/output pads arranged in a matrix of rows and columns, each of the input/output pads being connected to a first one of its row neighbors and a first one of its column neighbors by a two-state programmable interconnect element in series with a first three-state programmable interconnect element having first programming characteristics. A plurality of first conductors is generally disposed in a direction parallel to the rows, each of the rows having at least one of the first conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith, at least one of the first conductors segmented by at least one of the two-state programmable interconnect elements. A plurality of second conductors is generally disposed in a direction parallel to the columns, each of the columns having at least one of the second conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith. The second conductors form intersections with the fi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.